Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. As the size decreases, planar transistors increasingly suffer from the undesirable short-channel effect, especially “off-state” leakage current, which increases the idle power required by the device. In order to extend Moore's Law by continuing to create integrated circuit (IC) devices with ever smaller transistors and memory cells, semiconductor manufacturers have been developing several strategies.
Some of these strategies focus on non-planar devices. Some non-planar devices are referred to as FinFET devices, since the conducting channel in a FinFET transistor is wrapped by a thin silicon “fin”. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. Some non-planar devices are also referred to as multigate devices, since the channel is surrounded by several gates on multiple surfaces, allowing more effective suppression of “off-state” leakage current. Multiple gates allow enhanced current in the “on” state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance. Non-planar devices are more compact than devices with conventional planar transistors. This enables higher transistor density, which translates to smaller overall microelectronics.
One reason why non-planar devices are able to achieve higher transistor density and faster performance is that non-planar devices use all three dimensions to create transistors. Unlike traditional planar devices which use only surface areas along the top of the IC to form transistor gate channels, non-planar devices use surface areas along the thickness of the conductors in addition to surface areas along the top. This is why transistors in non-planar devices are able to switch faster, and why non-planar devices are able to pack in many more transistors per unit area.
Using all three dimensions to create transistors means that a non-planar IC design cannot be adequately represented by a collection of two dimensional polygons of uniform thickness. Using all three dimensions also means that a non-planar IC design cannot be properly verified unless verification tools extract parasitic capacitors and resistors along all three dimensions. This fact makes non-planar devices not only more difficult to manufacturer, but also more difficult to design and verify.
One possible solution is to represent each non-planar IC design as a collection of three dimensional objects. Such a representation is capable of yielding accurate models of transistors as well as parasitic elements. However, to three-dimensionally represent all physical elements in an IC requires far too much computing resources as well as engineering time. Another possible solution is to represent non-planar IC designs two dimensionally while approximating or extrapolating parasitic elements from the two dimensional polygons. This approach, though feasible in terms of cost and time, is not likely to yield sufficiently accurate verification models for non-planar devices that are densely filled with smaller and faster switching transistors.
There is therefore a need for an IC verification tool that accurately extracts parasitic elements from non-planar devices. Such an IC verification tool should be capable of associating three-dimensional properties of non-planar devices with two-dimensional representations of physical elements in the IC.